Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device for generating internal clock signals such as a DLL clock signal and a PLL clock signal to drive internal circuits.
In general, semiconductor devices including a double data rate synchronous dynamic random access memory (DDR SDRAM) device generate internal clock signals based on an external clock signal and use the internal clock signals as a reference to set various operational timing points therein. Therefore, the semiconductor device includes circuits to generate the internal clock signals, and the circuits include a phase locked loop (PLL), a delay locked loop (DLL) and so on.
FIG. 1 is a block diagram illustrating a conventional PLL.
Referring to FIG. 1, the PLL includes a phase/frequency detecting block 110, a charge pumping block 130, a loop filtering block 150, a voltage control oscillating block 170 and a resetting block 190.
The phase/frequency detecting block 110 detects phase/frequency of a feed-back PLL clock signal CLK_PLL based on a reference clock signal CLK_REF. The charge pumping block 130 controls a voltage level of a control voltage (V_CTR) node in response to an output signal of the phase/frequency detecting block 110. The loop filtering block 150 generates a control voltage V_CTR to the V_CTR node under the control of the charge pumping block 130. The voltage control oscillating block 170 generates the PLL clock signal CLK_PLL having a frequency corresponding to the control voltage V_CTR. The PLL clock signal CLK_PLL generated by the voltage control oscillating block 170 is fed back to the phase/frequency detecting block 110.
The PLL, having the above construction, performs a locking operation and generates the PLL clock signal CLK_PLL having a frequency the semiconductor device desires through the locking operation. When the locking operation is completed, the control voltage V_CTR is designed to have a voltage level for generating the PLL clock signal CLK_PLL having the desired frequency.
Meanwhile, the semiconductor device may have a standby mode as a low power mode to consume less power. The standby mode includes a self-refresh operation. When the semiconductor device enters into the standby mode, circuits consuming high power, such as the PLL, stop their operations. As a result, the power consumption of the semiconductor device is reduced. In performing a standby mode operation of the PLL, the phase/frequency detecting block 110, the charge pumping block 130 and the voltage control oscillating block 170 are controlled by a PLL enable signal EN_PLL. Therefore, when entering into the standby mode, each of the foregoing blocks is inactivated. In exiting out of the standby mode, each of the blocks is activated again.
The initial control voltage V_CTR is reset to a desired voltage level to allow the voltage control oscillating block 170 to perform its operation normally. According to an exemplary embodiment, the resetting block 190 performs a reset operation for the control voltage V_CTR and thus provides a supply voltage VDD to the V_CTR node in response to the PLL enable signal EN_PLL. The reset operation is performed in response to the PLL enable signal EN_PLL in case the PLL enters into the standby mode. At this time, the phase/frequency detecting block 110, the charge pumping block 130 and the voltage control oscillating block 170 are inactivated as described above.
However, the conventional PLL loses the locking information by the reset operation. In other words, the control voltage V_CTR has a voltage level for generating the PLL clock signal CLK_PLL having the desired frequency at the point of time when the locking operation is completed. That is, the voltage level of the control voltage V_CTR becomes the locking information when the locking operation is completed. However, since the V_CTR node is reset to the supply voltage VDD by the reset operation, the PLL loses the locked state. This means that the locking operation is restarted when exiting from the standby mode.
Time taken until the control voltage V_CTR has a desired voltage level through the locking operation, i.e., a locking completion time, may be a few micro-seconds, and the locking completion time is a factor when exiting from the standby mode as well as in an initial operation of the PLL. Nowadays, under circumstances that semiconductor devices are developed for a high-speed operation, the locking completion time is a concern in obtaining a high-speed operation of the semiconductor device.